Semiconductor microprocessors and large scale integrated circuits are manufactured by integrating elements such as metal-oxide-semiconductor (hereinafter referred to as “MOS”) field effect transistor (hereinafter referred to as “FET”) on a semiconductor substrate. Complementary MOSFETs (hereinafter referred to as “CMOS”) are generally basic elements (switch elements) of such integrated circuits. As the material for semiconductor substrates, silicon which is group IV semiconductor is mainly used. The degree of integration and performance of semiconductor microprocessors and large scale integrated circuits can be improved by reducing the size of transistors making up a CMOS. One of problems when reducing the size of the CMOS is an increase of power consumption. An increase in the number of CMOSs that can be mounted on one microchip and an increase of leakage current caused by a short channel effect can be cited as two of the major causes for the increase of power consumption. Of the two, the increase of leakage current brings about an increase of a supply voltage. Therefore, it is necessary to suppress the leakage current and reduce the operating voltage for each CMOS.
As an index indicating a switch characteristic of a CMOS, a subthreshold (mV/digit) is used. The subthreshold corresponds to a minimum drive voltage to drive the MOSFET into an ON state. The switch characteristic of the conventional MOSFET is based on a diffusion phenomenon of electrons and positive holes (carriers). Therefore, with the conventional MOSFET, a theoretical minimum value of a subthreshold slope is 60 mV/digit and it is not possible to realize a switch characteristic indicating a smaller subthreshold than this.
A tunnel FET (hereinafter referred to as “TFET”) is reported as a switch element that operates at a smaller subthreshold beyond this physical theoretical limit (e.g., see Non-Patent Literatures 1 and 2). Since the TFET has no short channel effect and can realize a high ON/OFF ratio at a low voltage, and is therefore considered as a prevailing candidate for a next-generation switch element. In recent years, TFETs using a nanowire are reported (e.g., see Patent Literatures 1 to 4).
Patent Literature 1 describes a TFET having a nanowire including an n-type doped region (source/drain region), undoped region (channel region) and p-type doped region (drain/source region). A gate dielectric layer is formed on the undoped region (channel region) and a gate electrode is arranged on the gate dielectric layer. This TFET is manufactured by doping an n-type dopant into a first region of the nanowire to form a source/drain region and doping a p-type dopant into a second region to form a drain/source region.
Patent Literatures 2 to 4 describe a TFET having a nanowire including an n-type doped region (source/drain region), undoped/low doped region (channel region) and p-type doped region (drain/source region). A gate dielectric layer is formed on an undoped/low doped region (channel region) and the gate electrode is arranged on the gate dielectric layer. In this TFET, a tunnel phenomenon occurs on a junction interface between the source region and the channel region. This TFET is manufactured by growing a nanowire using a metal catalyst placed on the substrate surface, then doping an n-type or p-type dopant to form the source region, channel region and drain region.